1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Related Art
In recent years, the increased performances and increased level of integration of the LSI are achieved, and a problem of an electromagnetic interference (EMI) has become to be intensified.
Although the countermeasure for the EMI have been presented by utilizing a packaging of a semiconductor device in the conventional technology, such type of countermeasure may also be a factor of an increase of cost and may cause a decrease of cost-competitiveness thereof. Therefore, countermeasures for the EMI in the interior of LSI have become to be often conducted as a method for reducing the increase of cost as much as possible.
Methods for providing countermeasures for the EMI of the interior of LSI generally classified into two types of methods: spectrum spread of an operating clock; and intensification of a power supply line.
Among these, a countermeasure by utilizing a capacity cell (a capacitor) has been often employed as a typical countermeasure for the EMI via the intensification of the power supply line.
However, when the capacity cell is utilized for the countermeasures for the EMI, embedded array and/or cell base IC, which are diffused from the underlying layer should have been employed in the conventional technology.
On the other hand, the miniaturization in the manufacturing process leads to manifesting a problem of an increase of the cost for manufacturing reticles. In such situation, master slice LSI have recently become to be employed, which can inhibits an increase of cost for manufacturing reticles by having a configuration of conducting a customization process for only the metal upper layers.
Among such types of technologies, a method for manufacturing a capacity cell is disclosed in Japanese Patent Laid-Open No. 1993-13,680 (H05-13, 680), in which a gate of an unused basic cell is coupled to a power supply electric potential (VDD) or a grounding electric potential (GND) to compose a capacitance of a gate polysilicon layer and an underlying gate oxide film and an inversion layer. Alternatively, a P+/N+ diffusion layer of the unused cell is coupled to the power supply electric potential (VDD) or to the grounding electric potential (GND) to compose a PN junction capacitance of the P+/N+ diffusion layer and a P/N well.
In addition, a method for manufacturing a capacitance is disclosed in Japanese Patent Laid-Open No. 1994-77,442 (H06-77,442), in which a polysilicon layer, a gate oxide film and an insulating film in an unused basic cell are removed at the time of completing the process for forming the polysilicon layer, and thereafter new gate oxide film and new polysilicon layer are formed again on that portion. Further, the formed polysilicon layer is divided into a PMOS side and a NMOS side, and the polysilicon of the PMOS side is coupled to the grounding electric potential (GND) and the polysilicon of the NMOS side is coupled to the power supply electric potential (VDD), respectively, to create inversion layers for the NMOS and the PMOS, respectively, thereby composing capacitances between the inversion layer and the polysilicon layer.
Further, a method for manufacturing a capacitance is disclosed in Japanese Patent Laid-Open No. 1999-274,441 (H11-274, 441), in which a sub-contact region for an interconnect adjacent to basic cell is employed to form a gate oxide film and a polysilicon layer, similarly as in the technology disclosed in Japanese Patent Laid-Open No. 1994-77,442. Further, the polysilicon of the PMOS side is coupled to the grounding electric potential (GND) and the polysilicon of the NMOS side is coupled to the power supply electric potential (VDD), respectively, to compose capacities between the inversion layers and the polysilicon layers. However, since sufficient capacitance for providing the EMI noise countermeasure can not be obtained in the capacitance of the sub-contact region, the process for DRAM is further utilized in the sub-contact region to form a trench structure, thereby achieving large capacitance.